1. Field of the Invention
The present invention relates to an input buffer circuit for receiving data that are supplied from the outside, and more particularly to an input buffer circuit that is used at a small-amplitude interface and to a semiconductor memory device that is provided with such an input buffer circuit.
2. Description of the Related Art
The use of semiconductor memory devices such as DRAM (Dynamic Random Access Memory) in mobile terminal devices such as portable telephones and PDAS (Personal Digital Assistants) in recent years has resulted in an even greater demand for reductions in current consumption. Progress is also being made in increasing the speed of semiconductor memory devices along with the development of higher speeds in CPUs, and input buffer circuits are being used that can both transfer data at high speeds and low voltage and meet the standards of, for example, SSTL (Stub Series Terminated Logic).
A differential amplifier is typically used in the input buffer circuit of a small-amplitude interface that accords with the SSTL standard. FIG. 1 shows the construction of such an input buffer circuit of the prior art.
As shown in FIG. 1, an input buffer circuit that is constructed with a differential amplifier of the prior art is a construction that includes: first transistor Q101 and second transistor Q102 having their gates connected in common and power supply voltage VDD supplied from their sources; third transistor Q103 having its drain connected to the drain of first transistor Q101; fourth transistor Q104 having its source connected in common to the source of third transistor Q103 and its drain connected to the drain of second transistor Q102; and fifth transistor Q105 that is inserted between the sources of third transistor Q103 and fourth transistor Q104 and ground potential VSS.
Connecting the gate and drain of second transistor Q102 causes first transistor Q101 and second transistor Q102 to form a current mirror circuit. Fifth transistor Q105 has power supply voltage VDD supplied to its gate, is always set to the on state, and supplies a prescribed operating current to first transistor Q101 to fourth transistor Q104, which make up a differential amplifier.
Reference voltage VREF, which is used for determining the level of the signal that is applied as input to the gate of third transistor Q103, is supplied to the gate of fourth transistor Q104, and, for example, clock enable signal CKE for determining whether system clock CLK that is supplied to the semiconductor memory device from the outside is valid or invalid, is applied as input to the gate of third transistor Q103. Clock enable signal CKE is used for power-down control or clock-suspend control that are known in the art, or for setting to the self-refresh mode that will be explained hereinbelow.
In the construction as described above, the input buffer circuit shown in FIG. 1 compares the level of clock enable signal CKE that is supplied from the outside with the level of reference voltage VREF and supplies a high level as clock enable signal CKEB from the drain of third transistor Q103, which is the output terminal, when clock enable signal CKE is low level. On the other hand, when clock enable signal CKE that is supplied from the outside is high level, the input buffer circuit supplies a low level as clock enable signal CKEB from the drain of third transistor Q103, which is the output terminal. The “B” (bar) of clock enable signal CKEB indicates that it is an inverted signal of signal CKE.
An input buffer circuit that is made up by the differential amplifier shown in FIG. 1 suffers little fluctuation in circuit characteristics due to variations in the threshold voltage VTH of the transistors, and provides stable operation for low-amplitude signals. However, there is the problem that a fixed short-circuit current flows even in the standby/halted state in which the input signal does not change. This short-circuit current that flows during the standby/halted state must be reduced in order to meet the demand in recent years for low power consumption in semiconductor memory devices.
To meet this requirement, constructions have been proposed such as Japanese Patent Laid-Open No. 294062/1997 that cuts off the power that is supplied to the differential amplifier in the halted or standby state. FIG. 2 shows the configuration of an input buffer circuit that is disclosed in Japanese Patent Laid-Open No. 294062/1997.
As shown in FIG. 2, the input buffer circuit that is disclosed in Japanese Patent Laid-Open No. 294062/1997 is a configuration that is provided with first switch transistor Q210 between differential amplifier 201 and power supply voltage VDD. First switch transistor Q210 is turned off by enable signal EN in the standby or halted state in which the input signal (CKE in FIG. 2) does not change, whereby the supply of power to differential amplifier 201 is halted. Because the level of this output (CKEB in FIG. 2) of differential amplifier 201 is indefinite at this time, second switch transistor Q211 is provided between the output terminal and ground potential VSS, and turning on second switch transistor Q211 fixes the output voltage of differential amplifier 201 to low level.
However, a DRAM is constructed such that data are held by the storage of electric charge in capacitors that are provided in memory cells. Accordingly, a refresh operation is necessary for reading, amplifying, and rewriting data that have been written within the maximum data holding time, i.e., the time interval that data can be held. Of the various refresh operations of this type, an operation in which the semiconductor memory device itself automatically executes a refresh operation is called self-refresh.
When the circuit that is disclosed in the above-described Japanese Patent Laid-Open No. 294062/1997 is used in, for example, an input buffer circuit to which the above-described clock enable signal CKE is received as input in a semiconductor memory device that requires a refresh operation, turning off the first switch transistor in the standby or halted state, which includes the self-refresh mode, can eliminate the short-circuit current of the differential amplifier and thus can reduce current consumption.
However, some semiconductor memory devices have a construction in which a clock enable signal CKE is used for the transition to the self-refresh mode and for the recovery from the self-refresh mode as described above. Thus, using the circuit that is disclosed in Japanese Patent Laid-Open No. 294062/1997 as the input buffer circuit for the clock enable signal CKE in such a semiconductor memory device has the disadvantage that the supply of power to the differential amplifier is halted and changes in clock enable signal CKE cannot be accepted, whereby recovery from the self-refresh mode cannot be achieved.